1. Field of the Invention
The present invention relates to a numerical control oscillator for frequency-converting a received signal into a demodulator input signal through a digital signal process, and a digital frequency converter and radio frequency unit including the same.
2. Description of the Related Art
A conventional numerical control oscillator (NCO) includes a phase data accumulator, and a memory (for example, a read only memory (ROM)) for outputting sine data corresponding to a phase calculated by the accumulator. Further, the NCO provides an output frequency defined as follows in Equation (1):F=(Fs×R)/2j  (1)
where, F is the output frequency, j is a phase word length, Fs is a sampling frequency, and R is an arbitrary integer.
In the case where a target frequency is obtained using a direct digital synthesizer (DDS) that digital/analog-converts and outputs an output signal from the NCO, the output frequency of the NCO can be changed at a 200 KHz step by adjusting the sampling frequency of the output signal from the NCO to 200 KHz×2j or extending the phase word length j (increasing the number of bits) to enhance a phase resolution, or frequency resolution, so that the difference between the target frequency and the output frequency of the NCO is within a range of an allowable deviation
For example, provided that the sampling frequency Fs is set to 153.6 MHz in a system where the output frequency F is 1.92 GHz and the allowable output frequency deviation Δ f is taken at a degree of precision of 0.1 ppm, the phase word length j will be taken as follows in Equation (2):
                                                        j              =                            ⁢                                                log                  2                                ⁡                                  (                                                            Fs                      /                      Δ                                        ⁢                                                                                  ⁢                    f                                    )                                                                                                        =                            ⁢                                                log                  2                                ⁡                                  (                                      153.6                    ×                                                                  10                        6                                            /                                              (                                                  1.92                          ×                                                      10                            9                                                    ×                          0.1                          ×                                                      10                                                          -                              6                                                                                                      )                                                                              )                                                                                                        ≈                            ⁢              19.61                                                          (        2        )            
It can be seen from the above Equation (2) that 20 bits are required to define the target phase word length j.
However, in the case where the phase word length j is extended, it is necessary to make the phase word length j equal to a word length k of the memory (the number of address bits of the memory) (j=k) in order to obtain an output signal of the NCO with no spurious effects caused by truncation of phase data. In the case of making the phase word length j larger than the memory word length k (j>k) in order to suppress an increase in memory size, it is necessary to requantize an address word length (memory word length) output from a phase calculator. This requantization causes the occurrence of an error ep of periodicity, which appears as a spurious in the output signal of the NCO (see Henry T Nicholas, III and Henry Samueli, “An Analysis of the Output Spectrum of Direct Digital Frequency Synthesizers in the Phase-Accumulator Truncation” in Proc. Annual Frequency Control Symposium, 1987, pp 495-502 (reference 1), for example).
On the other hand, known as a method for suppressing the spurious resulting from the requantization of the address word length from the phase calculator is, for example, a method based on an error feedback or error spread by design (see Jouko Vankka, “Spur. Reduction Techniques in Sine Output Direct Digital Synthesis” in IEEE International Frequency Control Symposium, 1996, pp 951-959 (reference 2), for example). However, as disclosed in reference 1, although the spurious is generated in the output signal due to the requantization of the address word length from the phase calculator, the phase word length j inevitably becomes larger than the memory word length k in order to suppress an increase in memory size.
Further, the techniques disclosed in reference 2 are disadvantageous in that additional circuits are required besides the original target circuits, resulting in an increase in circuit size even though the memory size is not increased. The method for suppressing the spurious using the error spread by design involves an increase in noise level (noise floor), so it is not necessarily effective.
Moreover, setting the sampling frequency to 2j times a desired frequency step makes it difficult to generate a reference frequency.